Adata AD2800E001GOU2 Fiche technique

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General Description
The ADATA’s ADQVD1A08 is a 128Mx64 bits 1GB(1024MB) DDR2-800(CL4) SDRAM EPP memory module,
The SPD is programmed to JEDEC standard latency 800Mbps timing of 5-5-5-18 at 1.8V. The module is composed
of eight 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP (TSOP)
package on a 240pin glass–epoxy printed circuit board.
The ADQVD1A08 is a Dual In-line Memory Module and intended for mounting onto 240-pins edge connector
sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are
possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow
the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Features
• Power supply (Normal): VDD & VDDQ = 1.8V ± 0.1V
• 1.8V (SSTL_18 compatible) I/O
• EPP (Enhanced Performance Profiles) support
• Timing Reference
- DDR2 800 CL5-5-5-18 at 1.8V
- DDR2 800 CL4-4-4-12 at 2.0V (EPP Profile 1)
- DDR2 800 CL4-4-4-11 at 2.0V (EPP Profile 2)
• Burst Length: 4, 8
• Programmable Additive Latency: 0, 1, 2, 3, 4
• Bi-directional, differential data strobe (DQS and /DQS)
• Differential clock input (CK, /CK) operation
• DLL aligns DQ and DQS transition with CK transition
• Double-data-rate architecture.
Auto & Self refresh
Average Refresh period 7.8µs
• Off-Chip Driver (OCD) Impedance Adjustment
• On Die Termination (ODT)
• Lead-free products are RoHS compliant
• EEPROM VDDSPD=3.3V (Typical)
• PCB Height 30.00mm (1.181”), Single sided component
• Clock Cycle Time (tCK):
- DDR2-800 tCK=2.5ns
• Refresh to Active/Refresh Command Time (tRFC): 127.5ns
ADQ
VD
1A08
DDR2-800+(CL4) 240-Pin EPP U-DIMM
1GB (128M x 64-bits)
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Page 1 - 1GB (128M x 64-bits)

General Description The ADATA’s ADQVD1A08 is a 128Mx64 bits 1GB(1024MB) DDR2-800(CL4) SDRAM EPP memory module, The SPD is programmed to JEDEC s

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